Phúc lợi dành cho bạn

  • Regularly trained and professionally oriented; 100% support of course fees

  • Social insurance and health insurance according to labor law

  • Review salary increase every 6 months according to work performance

  • Join team building, picnic, vacation

  • To participate in festivals and celebrate monthly birthdays

  • Especially, you can participate in Korean language lessons for free

Mô tả công việc

  • Develop and verify timing constraints based on the design specification; and build the synthesis environment to synthesize digital, mix-signal chips in advanced process nodes.
  • Derive timing signoff factors to check the design timing with MCMM (multi corners multi modes).
  • Work with RTL design engineers to perform STA at a large million gates design; to detect mismatch issues in RTL, build the constraint, optimize the circuit, and analyze timing; to optimize and determine the critical paths; and to provide the suggestion to RTL design engineers.
  •  Support to RTL design engineers in running Formality on ECO netlist; debug mismatched errors of the ECO netlist; and debug timing violations.
  • Work with layout engineersto isolate and identify the worst placement; to choose an optimized cell layout structure; and support the timing report, ECO fixing.
  • Support DFT engineers to implement DFT test flow including scan insertion, MBIST, scan compress/decompress for pin limited design, etc.
  • Develop working methodologies which includes RTL synthesis flow, DFT insertion flow and low power synthesis flow by using industry standard EDA tools.
  • Use ASICs CAD support for multi-VDD designs and make use the benefits of the power-intent designs using UPF.
  • Support project managers with effort estimations and resource planning.
  • Support team leader in coaching, training and development team members.

Yêu cầu công việc

  • University and above
  •  Major Electrical and Electronics, Computer science
  • Experience Not required Experience (Accept Fresher)
  • Experience in multiple clocks designs and low power design such as: Dynamic power optimization, MultiVt optimization, Clock gating, Dynamic and Adaptive
  • Voltage Frequency Scaling.
  • Excellent in manipulate primetime TCL script to generate timing report for a large design.
  • Deep knowledge of: synthesis, timing, equivalent checks, RC-extraction, noise, power, UPF, etc.
  • Experienced in using EDA tools such as: Design Compiler, Power Compiler, Formality, Primetime, Design For Test, TetraMax, etc.
  • Good knowledge in Design For Test implementation.
  • Good communication and interpersonal skills:
  • Good at English
  • Logical thinking
  • Research and apply new technology
  • Analytic and troubleshoot problem
  • Careful
  • Ability to multi-task and can work under deadline pressure.

COASIA SEMI VIỆT NAM

  • Quy mô công ty:
    50 - 99
  • Địa chỉ:
    Tầng 14, Khối A, tòa nhà Sông Đà, đường Phạm Hùng, Phường Mỹ Đình 1, Quận Nam Từ Liêm, Hà Nội
  • Website:
    https://coasiasemi.com/

CoAsia SEMI Ltd. provides the best semiconductor design service for all customers
who make the world one step further with innovative and useful technologies.
We offer a wide range of customer interfaces from Spec. to RTL, netlist, and GDS. We also offer IP customization, design technologies and platform solutions.
We serve as a Total Solution Provider that provides turnkey solutions including package, test, and quality control.

COASIA SEMI VIỆT NAM

Lương thỏa thuận

Hà Nội

18/07/2022

COASIA SEMI VIỆT NAM

Lương thỏa thuận

Hà Nội

18/07/2022

Từ khóa