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Mô tả công việc

Our team guarantee Gate netlist and SDC (Synopsys Design Constraint) qualification for Automotive SoCs. Our responsibility includes :

 

* Netlist qualification

 

  • Perform LSI ChipTop netlist checking as Renesas design rule such kind DFTcheck (Design For Test), HLDRC ( Highperformance Logic Design Rule Checker), STAcheck (Static Timing Analysis), FalseCheck, FV (logic equivalent check)
  • Monitor and control error judgement progress
  • Manage input/output design data b/t Front End vs Middle End and Back End.
  • Perform Logic ECO, DFT in RTL, synthesis, tessent DRC at Hierarchical level
  • Perform CT (combine test) Environment building

 

* SDC management for each of milestone

 

  • Hierarchical SDC creation
  • IPs level constraint integration
  • Delivery data to other design team with high quality
  • Support SDC debugging for project members
  • Monitor and control GCA (Galaxy constraint analysis) and PTE (PrimeTime error) judgement progress
  • ECO timing

 

* Work with other design teams (DFT, STA, Layout) to develop schedule and solve problem for timing closure until TapeOut

Yêu cầu công việc

  • Masters or Bachelor degree in Electrical or Computer Engineering.
  • Can Circuit/schematic analysis for debugging
  • Have STA (Static Timing Analysis) experience
  • Experience in Design Compile, Fusion, Genus, Conformal-lec, PrimeTime tool, VCS, Xcelium
  • Experience in Spyglass CDC, RTL-A as a plus
  • Experience in CT environment building as a plus
  • Experience in scripting languages such as C-Shell, Perl, Tcl, Visual Basic, Python, Jason, Ruby, Java
  • Good at management by Ms.Office tool such as Excel skill.
  • Good communication skills as well as problem solving skills.
  • Ability to work under pressure and multitask.
Ứng tuyển
HR1Tech's Client

HR1Tech's Client

  • Quy mô công ty:
    100 - 499
  • Địa chỉ:
    Hồ Chí Minh
  • Website:
    https://hr1tech.com/

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