Job Requirement
- Bachelor or Master Degree in Information Technology/ Computer Engineering/ Computer Science/ Telecoms/ Electronics
- 4+ years of experience as a relevant position
- Experience in scripting languages (PERL, shell, etc.)
- Knowledge about Hardware Verification languages (Verilog, SystemVerilog), SystemVerilog Assertion (SVA), Verification methodology (UVM, VMM)
- Solid knowledge of using EDA tools (ex: VCS/NC, Design-Compiler, Formality/Conformal)
- Basic knowledge of Formal verification, SVA, and TCL.