Job Description
- Implement RTL in Verilog/SystemVerilog, perform unit level testing, debug tests, SDC and UFP generation.
- Perform RTL Lint check, RTL synthesis, Equivalence checking, CDC checking and support Static Timing Analysis.
- Resolve technical issues in developing digital blocks, gate level simulation, power and static timing analysis with team members.
- Work with the verification team for a test plan/strategy to meet all functional requirements and performance.
- Work with the timing and physical team for timing closure and meet power and area goals.