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Job Description

Our team is performing design and verification for system IP (CPG, SYSC) as the below steps:

 

  • Make DRBFM, target specification, implementation specification.
  • Create clock/reset structure for whole SoC
  • Generate/coding full or a part of IP.
  • Perform UT and CT verification.
  • Perform synthesis and checkers (HLDRC, DFTcheck, STAcheck).
  • Perform test point insertion, Meta-FF and TMR.
  • Generate UPF for verification, implementation and physical

Job Requirement

  • Good knowledge about verification (UT, CT).
  • Familiar with simulator/debuger VCS/Verdi/XLM/Indago
  • Familiar with DC/FC
  • Basic knowledge about Formal verification.
  • Basic knowledge about SVA.
  • Basic knowledge about TCL.
  • Have knowledge about Verilog and UPF.
  • Have knowledge about Clock/Reset/Power at System level.
  • Knowledge about SystemVerilog and UVM is a plus.
  • Knowledge about Python is a plus
Apply now
HR1TECH

HR1TECH

  • Company size:
    100 - 499
  • Your address:
    Hồ Chí Minh
  • Website:
    https://hr1tech.com/

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